A reduction of the size and the inherent features of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the transistor and one of the inherent characteristics thereof, modulating a length of a channel region underlying a gate between a source and drain of the transistor alters a resistance associated with the channel region, thereby affecting a performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor.
In an environment of a transistor with a recessed source and drain (i.e., the regions of the source and drain are located below an upper surface of a substrate forming the foundation therefor), spacers about the gate may aid in a definition of the length of the channel region. More particularly, a source/drain region of the source and drain is often formed by an ion implantation process employing the gate and spacers thereabout as a mask to define the respective source/drain regions. Thus, a width of the spacers about the gate directly impacts a dimension and location of the source/drain regions of the source and drain. The thinner or slimmer the spacers, the closer the source/drain regions of the source and drain are formed about the channel region. As a result, the length of the channel region is reduced and the source-to-drain resistance is also reduced, thereby potentially augmenting a performance of the transistor.
To further enhance transistor performance, strain may be introduced in the channel region of the transistor to improve carrier mobility. Generally, it is desirable to induce a tensile strain in the channel region of a N-type metal oxide semiconductor (“NMOS”) device in a source-to-drain direction, and to induce a compressive strain in the channel region of a P-type metal oxide semiconductor (“PMOS”) device in a source-to-drain direction.
A typical technique of creating the strain includes depositing a high stress film over a transistor formed over and within a substrate after the transistor is constructed. The high stress film or stressor exerts significant influence on the channel region, modifying a silicon lattice spacing in the channel region, and thus introducing strain therein. In this case, the stressor is deposited over the transistor. This approach is described in detail by A. Shimizu, et al., in a publication entitled “Local Mechanical Stress Control (LMC): A New Technique for CMOS Performance Enhancement,” pp. 433-436, published in the Digest of Technical Papers of the 2001 International Electron Device Meeting, which is incorporated herein by reference.
In accordance with the design features of the transistor, employing slim spacers about the gate of the transistor may augment a strain within the channel region thereof. As mentioned above, a prevalent method of introducing the strain is to deposit a high stress film over the transistor. Thus, if the spacers about the gate are thin, the high stress film (for instance, a contact etching stop layer) is deposited in closer proximity to the channel region. Consequently, the high stress film can exert a higher level of strain within the channel region thereby augmenting a strain effect within the channel region of the transistor.
While the advantages of incorporating slim spacers into transistors (or any semiconductor device) appear decisive, there are limitations associated with slim spacers about the gate of the transistor. One of the more prevalent limitations is that slim spacers about the gate necessarily allow a silicide region formed over the source and drain of the transistor to be in closer proximity to the channel region of the transistor. If the silicide region diffuses through a lightly doped drain (which is typically adjacent the channel region) of the source or the drain, an electrical path may be created through the source or drain via the silicide region to the channel region. As a result, the silicide region may create a short circuit with the channel region thereby potentially providing a silicide spike within the transistor.
Accordingly, what is needed in the art is a semiconductor device that may incorporate slim spacers about the gate thereof to take advantage of the benefits associated with a channel region having a reduced length while at the same time overcoming the deficiencies of the prior art.